Nasiri-Fabrication

Nasiri-Fabrication

Nasiri-Fabrication Process

The Nasiri-Fabrication Process, patented by InvenSense, uses a wafer-to-wafer bonding process that allows for direct integration of the fabricated MEMS wafers to any off-the-shelf CMOS wafer at the wafer level. Although the wafer bonding process uses off-the-shelf wafer bonding equipment, the bonding process itself is proprietary and patented by InvenSense and allows for a eutectic bonding of the MEMS wafers directly to the aluminum layer on the CMOS wafer without the addition of other material layers on top of the aluminum. This process leads to smaller package footprints and package heights. In one bonding step, Nasiri-Fabrication provides for wafer-scale integration by making electrical interconnects between the MEMS and CMOS, and wafer scale packaging by simultaneously providing a fully hermetic seal of the MEMS structures. The seal does not require the use of frit glass or getters and provides a reliable and controlled vacuum level over the full life of the product. The inherent materials used are not susceptible to outgassing.

InvenSense NasiriFabrication WithText

Wafer level integration of MEMS, electronics and micro packaging addresses the widely recognized high package and test costs associated with MEMS devices. Each die is fully encapsulated and is packaged using standard, low-cost QFN packages. Furthermore, the bonded wafer has full functionality, allowing each die to be tested at wafer probe. Wafer-level testing provides mapping information for timely feedback to the foundries for improved process control, and provides device-level traceability by programming information at wafer sort test. Using conventional high speed testers at the wafer probing level reduces the test costs associated with custom testers needed for sensitivity calibration of packaged parts.

There is no overhead for the bond pads. The efficiencies of this packaging technology, combined with the reduced wafer-level testing costs, leads to a design optimized for the size and cost constraints of the consumer electronics market. The wafer-level bonding technique provides the only viable solution for MEMS+CMOS chip-scale package (CSP) design for reduced cost and solution size.

The gyroscope, more so than most technologies, depends on the qualities and characteristics of its fabrication platform to meet the size, cost and performance requirements of highvolume consumer electronics products. Surface micromachining is a stable, well-proven fabrication technology that has seen success with high-volume consumer MEMS microphones and accelerometers. However, the unique design challenges of a MEMS gyroscope require further advancements in MEMS fabrication to achieve the same success seen by the accelerometer.

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