Peripheral Component Interconnect

Infobox Computer Hardware Bus
name = PCI
fullname = peripheral component interconnection

---

caption = Five 5V 32-bit PCI expansion slots on a motherboard
invent-date = July 1993
invent-name = Intel
super-date = 2004
super-name = PCI Express
width = 32 or 64
pin count = 124 32bit
numdev = 1 per slot
capacity = 133 MB/s
style = m
hotplugging = optional and rareThe Peripheral Component Interconnect, or PCI Standard (commonly PCI), specifies a computer bus for attaching peripheral devices to a computer motherboard. These devices can take any one of the following forms:
*An integrated circuit fitted onto the motherboard itself, called a "planar device" in the PCI specification.
*An expansion card that fits into a socket.

The PCI bus is common in modern PCs, where it has displaced ISA and VESA Local Bus as the standard expansion bus, but it also appears in many other computer types. The bus is being succeeded by PCI Express, which launched in 2004 and offers much higher bandwidth. As of 2007 the PCI standard is still used by many legacy and new devices that do not require the higher bandwidth of PCI-E. New computers are also still provided with ample PCI slots.

The PCI specification covers the physical size of the bus (including wire spacing), electrical characteristics, bus timing, and protocols. The specification can be purchased from the PCI Special Interest Group (PCI-SIG).

Typical PCI cards used in PCs include: network cards, sound cards, modems, extra ports such as USB or serial, TV tuner cards and disk controllers. Historically video cards were typically PCI devices, but growing bandwidth requirements soon outgrew the capabilities of PCI. Today PCI video cards are uncommon and principally at the lower end of the market. However, the advent of Windows Vista with its strenuous requirements for its Aero interface, combined with many PCs lacking AGP or PCI Express slots, means that there are now many "Vista Ready" PCI graphics cards released [Get Vista's Aero Glass eye candy on AGP and PCIe-less PCs: DX9.0 PCI cards for your dinosaur. By Fernando Cassia: Wednesday, 15 November 2006, 9:33 AM. Retrieved July 18, 2008 from http://www.theinquirer.net/en/inquirer/news/2006/11/15/get-vistas-aero-glass-eye-candy-on-agp-and-pcie-less-pcs] , with a claim by one manufacturer that "In fact, what we have experienced is growing demand for PCI graphics upgrades, because the PCI card works in all PCs…Past, Present and Future." [VisionTek™ Introduces First Retail RADEON®™ X1300 256MB PCIin North America. Retrieved July 19, 2008 from http://www.visiontek.com/press/09-01-06.html] At Computex 2008, a number of cutting-edge GeForce 8 based cards were released. [Albatron Retrotechnology -"PCI" graphics alive and kickin' with GeForce 8 Series GPUs!. Retrieved July 18, 2008 from http://www.pcstats.com/releaseview.cfm?ReleaseID=1740]

Many devices traditionally provided on expansion cards are now commonly integrated onto the motherboard itself, meaning that modern PCs often have no cards fitted. However, PCI is still used for certain specialized cards, although many tasks traditionally performed by expansion cards may now be performed equally well by USB devices.

History

Work on PCI began at Intel's Architecture Lab circa 1990. PCI 1.0, which was merely a component-level specification, was released on June 22, 1992. PCI 2.0, which was the first to establish standards for the connector and motherboard slot, was released on April 30, 1993. PCI 2.1 was released on June 1, 1995.

PCI was immediately put to use in servers, replacing MCA and EISA as the server expansion bus of choice. In mainstream PCs, PCI was slower to replace VESA Local Bus (VLB), and did not gain significant market penetration until late 1994 in second-generation Pentium PCs. By 1996 VLB was all but extinct, and manufacturers had adopted PCI even for 486 computers. [VLB was designed for 486-based systems, yet even the more generic PCI was to gain prominence on that platform.] EISA continued to be used alongside PCI through 2000. Apple Computer adopted PCI for professional Power Macintosh computers (replacing NuBus) in mid-1995, and the consumer Performa product line (replacing LC PDS) in mid-1996.

Later revisions of PCI added new features and performance improvements, including a 66 MHz 3.3 V standard and 133 MHz PCI-X, and the adaptation of PCI signaling to other form factors. Both PCI-X 1.0b and PCI-X 2.0 are backward compatible with some PCI standards. With the introduction of the serial PCI Express standard in 2004, motherboard manufacturers have included progressively fewer PCI expansion slots in favor of the new standard. Although it is still common to see both interfaces implemented side-by-side, traditional PCI is likely to slowly die out in coming years.

Auto Configuration

PCI provides two separate 32-bit or 64-bit address spaces corresponding to the memory and I/O port address spaces of the x86 processor family. Addresses in these address spaces are assigned by software. A third address space, called the PCI Configuration Space, which uses a fixed addressing scheme, allows software to determine the amount of memory and I/O address space needed by each device. Each device can request up to six areas of memory space or I/O port space via its configuration space registers.

In a typical system, the firmware (or operating system) queries all PCI buses at startup time (via PCI Configuration Space) to find out what devices are present and what system resources (memory space, I/O space, interrupt lines, etc.) each needs. It then allocates the resources and tells each device what its allocation is.

The PCI configuration space also contains a small amount of device type information, which helps an operating system choose device drivers for it, or at least to have a dialogue with a user about the system configuration.

Devices may have an on-board ROM containing executable code for x86 or PA-RISC processors, an Open Firmware driver, or an EFI driver. These are typically necessary for devices used during system startup, before device drivers are loaded by the operating system.

In addition there are PCI Latency Timers that are a mechanism for PCI Bus-Mastering devices to share the PCI bus fairly. "Fair" in this case means that devices won't use such a large portion of the available PCI bus bandwidth that other devices aren't able to get needed work done. Note, this does not apply to PCIE.

"How this works is that each PCI device that can operate in bus-master mode is required to implement a timer, called the Latency Timer, that limits the time that device can hold the PCI bus. The timer starts when the device gains bus ownership, and counts down at the rate of the PCI clock. When the counter reaches zero, the device is required to release the bus. If no other devices are waiting for bus ownership, it may simply grab the bus again and transfer more data." [cite web
title = PCI Latency Timer Howto
publisher = Reric.NET by Eric Seppanen
date = 2004-11-14
url = http://www.reric.net/linux/pci_latency.html
accessdate = 2008-07-17]

There is a PCI Latency Tool available, you can use a search engine to locate the latest version. This tool will allow you to change/set the latency for any PCI card that allows it.

Interrupts

Devices are required to follow a protocol so that the interrupt lines can be shared. The PCI bus includes four interrupt lines, all of which are available to each device. However, they are not wired in parallel as are the other traces. The positions of the interrupt lines rotate between slots, so what appears to one device as the INTA# line is INTB# to the next and INTC# to the next. Single-function devices use their INTA# for interrupt signaling, so the device load is spread fairly evenly across the four available interrupt lines. This alleviates a common problem with sharing interrupts.

PCI bridges (between two PCI buses) map the four interrupt traces on each of their sides in varying ways. Some bridges use a fixed mapping, and in others it is configurable. In the general case, software cannot determine which interrupt line a device's INTA# pin is connected to across a bridge. The mapping of PCI interrupt lines onto system interrupt lines, through the PCI host bridge, is similarly implementation-dependent. The result is that it can be impossible to determine how a PCI device's interrupts will appear to software. Platform-specific BIOS code is meant to know this, and set a field in each device's configuration space indicating which IRQ it is connected to, but this process is not reliable.

PCI interrupt lines are level-triggered. This was chosen over edge-triggering in order to gain an advantage when servicing a shared interrupt line, and for robustness: edge triggered interrupts are easy to miss.

Later revisions of the PCI specification add support for message-signalled interrupts. In this system a device signals its need for service by performing a memory write, rather than by asserting a dedicated line. This alleviates the problem of scarcity of interrupt lines. Even if interrupt vectors are still shared, it does not suffer the sharing problems of level-triggered interrupts. It also resolves the routing problem, because the memory write is not unpredictably modified between device and host. Finally, because the message signaling is in-band, it resolves some synchronization problems that can occur with posted writes and out-of-band interrupt lines.

PCI Express does not have physical interrupt lines at all. It uses message-signalled interrupts exclusively.

Conventional hardware specifications

These specifications represent the most common version of PCI used in normal PCs.
*33.33 MHz clock with synchronous transfers
*peak transfer rate of 133 MB/s (133 million bytes per second) for 32-bit bus width (33.33 MHz × 32 bits ÷ 8 bits/byte = 133 MB/s)
*peak transfer rate of 266 MB/s for 64-bit bus width
*32-bit or 64-bit bus width
*32-bit address space (4 gigabytes)
*32-bit I/O port space
*256-byte configuration space
*5-volt signaling
*reflected-wave switching

Variants

Conventional

*Later versions of PCI allow (and in the latest versions require) 3.3 V slots (keyed differently) on motherboards and allow for cards that are either double keyed for both voltages or even 3.3 V only.

*PCI 2.2 allows for 66 MHz signalling at 3.3 volt signal voltage (peak transfer rate of 533 MB/s), but at 33 MHz both 5 volt and 3.3 volt signal voltages are still allowed. Power rails to provide 3.3 volt "supply" voltage are now mandatory. [http://www.pcisig.com/specifications/conventional/conventional_pci/2_2sum1215.pdf PCI-SIG Changes between PCI 2.1 and PCI 2.2]
*PCI 2.3 permits use of 3.3 volt and universal keying, but does not allow 5 volt keyed add in cards.
*PCI 3.0 is the final official standard of the bus, completely removing 5-volt capability.
*PCI-X increases the maximum signaling frequency to 133 MHz (peak transfer rate of 1066 MB/s) and revises the protocol.
*PCI-X 2.0 permits a 266 MHz rate (peak transfer rate of 2133 MB/s) and also 533 MHz rate (4266 MB/s - 32x the original PCI bus), expands the configuration space to 4096 bytes, adds a 16-bit bus variant (allowing smaller slots where space is tight) and allows for 1.5 volt signaling
*Mini PCI is a form factor of PCI 2.2 for use mainly inside laptops
*CardBus is a PC card form factor for 32-bit, 33 MHz PCI
*CompactPCI uses Eurocard-sized modules plugged into a PCI backplane.
*PC/104-Plus is an industrial bus that uses the PCI signal lines with different connectors.

Physical card dimensions

Full-size card

The original "full-size" PCI card is specified as a height of 107 mm (4.2 inches) and a depth of 312 mm (12.283 inches). The height includes the edge card connector. However, most modern PCI cards are half-length or smaller (see below) and many PCs cannot fit a full size card.

Backplate card

In addition to these dimensions the physical size and location of a card's backplate are also standardized. The backplate is the part that fastens to the card cage to stabilize the card and also contains external connectors, so it usually attaches in a window so it is accessible from outside the computer case.

The card itself can be a smaller size, but the backplate must still be full-size and properly located so that the card fits in any standard PCI slot.

Half-length extension card (de-facto standard)

This is in fact the practical standard now - the majority of modern PCI cards fit inside this length.

*Width: 0.6 inches (15.24 mm)
*Depth: 6.9 inches (175.26 mm)
*Height: 4.2 inches (106.68 mm)
*

Low-profile (half-height) card

The PCI organization has defined a standard for "low-profile" cards, which basically fit in the following ranges:
* Height: 1.42 inches (36.07 mm) to 2.536 inches (64.41 mm)
* Depth: 4.721 inches (119.91 mm) to 6.6 inches (167.64 mm)The bracket is also reduced in height, to a standard 3.118 inches (79.2 mm).

These cards may be known by other names such as "slim".

* [http://www.pcisig.com/news_room/faqs/#low_profile_pci Low Profile PCI FAQ]
* [http://www.pcisig.com/specifications/conventional/conventional_pci/lowp_ecn.pdf Low Profile PCI Specification]

Mini PCI

This is a specialist version of PCI slot intended for laptops and the like.

Other physical variations

Typically consumers systems specify "N x PCI slots" without specifying actual dimensions of the space available. In some small form-factor systems, this may not be sufficient to allow even "half-length" PCI cards to fit. Despite this limitation, these systems are still useful because many modern PCI cards are considerably smaller than half-length.

Card keying

Typical PCI cards present either one or two key notches, depending on their signaling voltage. Cards requiring 3.3 volts have a notch 56.21mm from the front of the card (where the external connectors are) while those requiring 5 volts have a notch 104.47mm from the front of the card. So called "Universal cards" have both key notches and can accept both types of signal.

ee also

* List of device bandwidths (A useful listing of device bandwidths that includes PCI)
* AMBA specification
* Industry Standard Architecture (ISA)
* Extended Industry Standard Architecture (EISA)
* Micro Channel architecture (MCA)
* Mini PCI
* NuBus
* Zorro II and Zorro III
* VESA Local Bus (VLB)
* Accelerated Graphics Port (AGP)
* PCI Express (PCIe) - the successor of PCI from 2004 onwards
* PCI-X
* PCI Configuration Space

References

External links

* [http://computer.howstuffworks.com/pci.htm How Stuff Works - PCI]
* [http://www.pcisig.com/home PCI SIG]
* [http://www.pcidatabase.com/index.php PCI Vendor and Device Lists]
*http://pciids.sourceforge.net PCI IDs.
* [http://members.datafast.net.au/dft0802/downloads.htm PCI and PCI32 utilities] , Craig Hart's freeware PCI Software suites and ID Database
* [http://tuxmobil.org/minipci_linux.html Linux with miniPCI cards]
* [http://pinouts.ru/Slots/PCI_pinout.shtml PCI bus pin-out and signals]
* [http://kmuto.jp/debian/hcl/index.cgi GNU/Linux PCI device driver check page]
* [http://www.4crawler.com/Developer/VisualWorkstation/PCI/index.shtml Brief overview of PCI power requirements and compatibility with a nice diagram.]
* [http://www94.web.cern.ch/hsi/s-link/devices/s32pci64/slottypes.html Good diagrams and text on how to recognize the difference between 5 volt and 3.3 volt slots.]