- OpenRISC
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OpenRISC is the original flagship project of the OpenCores community. This project aims to develop a series of general purpose open source RISC CPU architectures. The first (and currently only) architectural description is for the OpenRISC 1000, describing a family of 32 and 64-bit processors with optional floating point and vector processing support.[1]
A team from OpenCores provided the first implementation, the OpenRISC 1200, written in the Verilog hardware description language. The hardware design was released under the GNU Lesser General Public License, while the models and firmware were released under the GNU General Public License. A reference SoC implementation based on the OpenRISC 1200 was developed, known as ORPSoC (the OpenRISC Reference Platform System-on-Chip). A number of groups demonstrated ORPSoC and other OR1200 based designs running on FPGA.[2][3]
Contents
Instruction set
The instruction set is a reasonably simple example of a modern RISC using a 3-operand load-store architecture, with 16 or 32 general-purpose registers and a fixed 32-bit instruction length. The instruction set is mostly identical between the 32 and 64 bit versions of the specification, the main difference being the register width (32 or 64 bits) and pagetable layout. The OpenRISC specification includes all features common to modern desktop/server processors: a supervisor mode and virtual memory system, optional read, write and execute control for memory pages, and instructions for synchronization and interrupt handling between multiple processors.
As of October 2011, there are still some minor details in the 64-bit specification that are incomplete or ambiguous.
Another notable feature is a rich set of SIMD instructions intended for digital signal processing.
Implementations
Most implementations are on FPGAs which give the possibility to iterate on the design at the cost of performance. As the OpenRISC 1000 is now considered stable the OpenCores project is trying to build a cost-efficient ASIC with this design to get improved performance[4]. They launched a call for donations in 2011 with the aim to produce the first ASIC in Q1 2012[5].
Commercial implementations
Several commercial organizations have developed derivatives of the OpenRISC 1000 architecture, including the ORC32-1208 from ORSoC (who also maintain the opencores.org website) and the BA12, BA14 and BA22 from Beyond Semiconductor. Dynalith Systems provide the iNCITE FPGA prototyping board, which is capable of running both the OpenRISC 1000 and BA12. Flextronics International and Jennic Limited manufactured the OpenRISC as part of an ASIC.
More recently Cadence Design Systems have started using OpenRISC as a reference architecture in documenting tool chain flows (for example the UVM reference flow, now contributed to Accellera[6]).
Toolchain support
The OpenCores community have ported the GNU toolchain to OpenRISC to support development in C and C++. Using this tool chain the newlib and uClibc libraries have been ported to the processor. Dynalith provides OpenIDEA, a graphical development environment based on this tool chain.
The OR1K project provides an instruction set simulator, or1ksim. The flagship implementation, the OR1200, is an RTL model in Verilog HDL, from which a SystemC-based cycle-accurate model can be built in ORPSoC. A high speed model of the OpenRISC 1200 is also available through the Open Virtual Platforms (OVP) initiative set up by Imperas.
Operating system support
Linux support
Support for the mainline Linux kernel was gained in version 3.1.[7] The implementation merged in this release is the 32-bit OpenRISC 1000 family (or1k).[8]. Previously µClinux had been ported to the OpenRISC 1000 architecture, but this has now been superseded by the mainline port.
RTOS support
A number of real time operating systems have been ported to OpenRISC, including RTEMS, FreeRTOS and eCos.
See also
- OpenCores
- OpenRISC 1200
- Open Virtual Platforms
- OpenSPARC
- LEON
- LatticeMico32
References
- ^ Damjan Lampret et al., "OpenRISC 1000 Architecture Manual", Rev 1.3, 15 Nov 2007. Available from the OpenCores website [1]
- ^ Patrick Pelgrims, Tom Tierens and Dries Driessens, "Basic Custom OpenRISC System Hardware Tutorial: Embedded system design based upon Soft- and Hardcore FPGA’s", De Nayer Instituut, Hogeschool voor Wetenschap & Kunst, 2004. Available online [2]
- ^ Xiang Li and Lin Zuo, "Open source embedded platform based on OpenRISC and DE2-70", Masters dissertation, SoC program, KTH, Sweden. Available online [3]
- ^ OpenCores - Call for OpenRISC ASIC donations
- ^ OpenCores donation FAQ
- ^ UVM Reference Flow, Accellera website (undated).
- ^ "git.kernel.org - linux/kernel/git/torvalds/linux-2.6.git/tree - arch/openrisc/". git.kernel.org. http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=tree;f=arch/openrisc;hb=HEAD. Retrieved 17/10/2011.
- ^ "Linux 3.1". Kernel Newbies. http://kernelnewbies.org/Linux_3.1#head-37c60fa1253db74ce7d224718a71f5836bd5be09. Retrieved 17/10/2011.
External links
- OpenRISC main project page at the OpenCores Website
- GNU toolchain building guides
- Beyond Semiconductor commercial fabless semiconductor company founded by the developers of OpenRISC
- Dynalith Systems company website.
- Imperas company website.
- Flextronics International company website
- Jennic company website
- ORSoC company website. ORSoC also maintain the opencores.org website.
- Eetimes article
RISC-based processor architectures Altera Nios II · AMD 29000 · Apollo PRISM · Analog Devices Blackfin · ARM · Atmel AVR · Atmel AVR32 · Cambridge Consultants XAP · DEC Alpha · DLX · eSi-RISC · PA-RISC · Intel i960 · M32R · LatticeMico8 · LatticeMico32 · MIPS · Motorola 88000 · OpenRISC · Power ISA · S+core · SPARC · Renesas SuperH · Xilinx MicroBlaze · Xilinx Picoblaze · XMOS XCore XS1MicroBlaze · PicoBlaze · LatticeMico8 · LatticeMico32 · Nios · Nios II · OpenRISC · OpenSPARC · LEONCategories:- Open microprocessors
- Embedded microprocessors
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