Xtensa

Xtensa is a 32-bit microprocessor core designed by Tensilica.

Tensilica describes it as "a configurable, extensible and synthesizable processor core" ... "the first microprocessor architecture designed specifically to address embedded System-On-Chip (SOC) applications".

All Xtensa configurable processors have two essential features:
*Configurability - designers are offered a menu of checkbox and drop-down menu options so they can pick just the features they need.
*Extensibility - designers can add multi-cycle execution units, registers, register files, and much more using the Tensilica Instruction Extension (TIE) methodology, where the designer only has to specify and verify the functional behavior of the new data path and the RTL is automatically generated.

All of the tools, including the compiler (a hacked up egcs, which is essentially gcc from about 1997 to 1999), debugger and ISS (Instruction Set Simulator), are automatically updated to match the configuration options and all changes made in TIE. The matching tool set is generated by the Xtensa Processor Generator at the same time the new processor RTL is created.

Tensilica’s top-of-the-line product, Xtensa LX2 takes the configurable, extensible processor to the next level with RTL-equivalent bandwidth and exceptional computational performance. This highly flexible processor is ideal for DSP and data-intensive functions. Tensilica's Xtensa 7 configurable, extensible processor is optimized for low-power applications and is ideal for control and DSP operations.

Tensilica’s Xtensa LX2 processor takes application performance to new heights. It is the only processor core for system-on-chip (SOC) designs that provides the I/O bandwidth, compute parallelism, and low-power optimization equivalent to hand-optimized, RTL-designed non-programmable hardware blocks. With Tensilica’s unique XPRES Compiler and automated processor generator, every Tensilica customer is able to quickly generate a tailored version of the Xtensa LX2 optimized for their particular application, Ideal for handling traditional SOC embedded processor control tasks as well as compute-intensive datapath hardware tasks, the Xtensa LX2 processor is the basic building block for complex SOC design.

The Xtensa LX2 32-bit architecture features a compact instruction set optimized for embedded designs. The base architecture has a 32-bit ALU, up to 64 general-purpose physical registers, 6 special purpose registers and 80 base instructions including improved 16- and 24-bit (rather than 32-bit) RISC instruction encoding.

Using Tensilica’s Xtensa software-development tools, SOC designers can profile their application software, configure the Xtensa LX2 processor and add new instructions to optimize performance, all in a matter of hours.

Highlights of the Xtensa LX2 configurable processor core

*Lower power – The processor employs fine-grain clock gating for every functional element, including designer-defined functions. The minimum configuration dissipates 0.05 mW/MHz in a representative 130 nm process technology - less than half the power consumption of other popular embedded processor cores.

*I/O throughput at RTL speeds – SOC designers can choose one or two 128-bit wide load/store units. If that isn’t enough, you can add direct-access ports and queue interfaces that allow the Xtensa LX2 processor to communicate as fast and flexibly as RTL blocks.

*Outstanding compute performance - The Xtensa LX2 processor’s innovative FLIX (Flexible Length Instruction Xtensions) architecture (a VLIW implementation without the associated code bloat) allows designers to pack multiple operations more efficiently into wider words.

*Better interfaces to on-chip memories - Designers can select a longer pipeline that adds a clock cycle to each memory access, which permits the processor to use slower memories even when running at high clock rates. Local memories can be as large as 4 megabytes with optional parity or ECC. All local memories and the main system bus can have independent interface widths.

*The XPRES Compiler - Tensilica’s XPRES Compiler is a powerful synthesis tool that quickly creates tailored processor descriptions for the Xtensa LX2 processor from native C/C++ code.

Tensilica’s Xtensa 7 processor is also a configurable, extensible and synthesizable 32-bit RISC processor core. The Xtensa 7’s architecture was designed, from the start, to enable designers to tailor each implementation to match the application requirements for the target SOC.

Xtensa 7 Features

*32-bit synthesizable RISC architecture with 5-stage pipeline, 16/24-bit instruction encoding with modeless switching
*Designer-configurable processor options (MMU/MPU, local memory types and sizes, hardware multipliers, etc.)
*Optional designer-defined, application-specific instructions can be added to the base architecture
*XPRES Compiler automates generation of instruction extensions from C/C++ algorithms
*Automated fine and coarse-grain clock gating for ultra-low power
*Local memories can include parity or ECC.

Benefits of the Xtensa architecture

*Extremely efficient base architecture that is smaller, lower power, and has better code density than other 32-bit processors
*Application-specific instruction extensions provide orders-of-magnitude application performance improvements, eliminating the need for RTL blocks from SOCs
*Pre-verified, correct-by-construction RTL generation lowers verification efforts
*Reduces design risk with post-silicon programmability using processors instead of RTL blocks.

Create an Optimized Processor in Minutes

By selecting and configuration predefined elements of the architecture and by inventing completely new instructions and hardware execution units, the Xtensa 7 processor can deliver performance levels orders of magnitude faster than standard 32-bit processor cores. Designers define new instructions utilizing the Tensilica Instruction Extension (TIE) methodology, adding Verilog-like descriptions of datapaths, execution units, and register files that can deliver performance, area, and power characteristics equivalent to custom logic design.

Or, the designer can use the XPRES Compiler to analyze the C/C++ algorithm and automatically suggest configuration options and extensions that will run that algorithm faster. Compared to traditional hardware design, Xtensa processors deliver similar quality of results with the added benefits of accelerated design time and post-silicon software programmability.

External links

* [http://www.tensilica.com/products/overview.htm Tensilica products overview]
* Tensilica Instruction Extension