Runway bus

The Runway bus is a front side bus developed by Hewlett-Packard for use by its PA-RISC microprocessor family. The Runway bus is a 64 bit wide, split transaction, time multiplexed address and data bus running at 120 MHz. This scheme was chosen by HP as they determined that a bus using separate address and data wires would have only delivered 20% more bandwidth for a 50% increase in pin count, which would have made microprocessors using the bus more expensive. The Runway bus was introduced with the release of the PA-7200 and was subsequently used by the PA-8000, PA-8200, PA-8500, PA-8600 and PA-8700 microprocessors. Early implementations of the bus used in the PA-7200, PA-8000 and PA-8200 had a theoretical bandwidth of 768 MT/s. Beginning with the PA-8500, the Runway bus was revised to transmit on both rising and falling edges of the 120 MHz clock signal, which increased its theoretical bandwidth to 1.536 GT/s. The Runway bus was succeeded with the introduction of the PA-8800, which used the Itanium 2 bus.

Most machines use the Runway bus to connect the CPUs directly to the IOMMU (Astro, U2/Uturn or Java) and memory.However, the N class and L3000 servers use an interface chip called Dew to bridge the Runway bus to the Merced bus that connects to the IOMMU and memory.

References

* A High Performance, Low Cost Multiprocessor Bus for Workstations and Midrange Servers by William R. Bryg, Kenneth K. Chan, and Nicholas S. Fiduccia. Article 2, Hewlett Packard Journal, February 1996.
* PA-8500's 1.5M Cache Aids Performance by Linley Gwennap. The Microprocessor Report, November 17, 1997.

ee also

*List of device bandwidths