Hardware verification language
- Hardware verification language
A Hardware Verification Language, or HVL, is a programming language used to verify the designs of electronic circuits written in a hardware description language. HVLs typically include features of a high-level programming language like C++ or Java as well as features for easy bit-level manipulation similar to those found in HDLs.
OpenVera, Specman e, and SystemC are the most commonly used HVLs, while SystemVerilog attempts to combine HDL and HVL constructs into a single standard.
See also
*OpenVera
*Specman
*SystemC
*SystemVerilog
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