Four-phase logic

Four-phase logic

Four-phase logic is a type of, and design methodology for, dynamic logic; it enabled non-specialist engineers to design quite complex ICs, using either PMOS or NMOS processes.

History

In 1968 Lee Boysel [http://en.wikipedia.org/wiki/Four_Phase_Systems_AL1] , founder of Four Phase Systems, previously a designer at Fairchild Semiconductor, published an article "Adder On a Chip: LSI Helps Reduce Cost of Small Machine" in Electronics magazine. Papers from Y. T. Yen, J. L. Seely, L. Cohen, R. Rubinstein, and F. Wanlass also appear around this time.

tructure

There are basically two types of logic gate - a '1' gate and a '3' gate. These differ only in the clock phases used to drive them. A gate can have any logic function; thus potentially each and every gate has a customised layout. An example 2-input NAND 1 gate and an inverter 3 gate, together with their clock phases (the example uses NMOS transistors), are shown below:

The ø1 and ø3 clocks need to be non-overlapping, as do the ø2 and ø4 clocks. Considering the 1 gate, during the ø1 clock high time (also known as the precharge time) the output C precharges up to V(ø1)-Vth, where Vth represents the threshold of the precharge transistor. During the next quarter clock cycle (the sample time), when ø1 is low and ø2 is high, C either stays high (if A or B are low) or C gets discharged low (if A and B are high).

The A and B inputs must be stable throughout this sample time. The output C becomes valid during this time - and therefore a 1 gate output can't drive another 1 gate's inputs. Hence 1 gates have to feed 3 gates and they in turn have to feed 1 gates.

One more thing is useful - 2 and 4 gates. A 2 gate precharges on ø1 and samples on ø3:

and a 4 gate precharges on ø3 and samples on ø1.

Gate interconnection rules are: 1 gates can drive 2 gates and/or 3 gates; 2 gates can drive only 3 gates, 3 gates can drive 4 gates and/or 1 gates, 4 gates can drive only 1 gates:

Usage

Four-phase logic works well; in particular there are no race hazards because every combinatorial logic gate includes a register. It's worth noting that the layout does not require the bussing of any power supplies - only clock lines are bussed. Also, since the design technique is ratioless (cf. "static logic"), many designs can use minimum-size transistors.

There are some difficulties:
*The gate output is dynamic. This means that its state is held on capacitance at the gate output. But the output track can cross clock lines and other gate outputs, all of which can change the charge on the capacitor. In order that the gate output voltage remains at some safe 0 or 1 level during the cycle the amount of change has to be calculated and, if necessary, additional (diffusion) capacitance has to be added to the output node.
*For a given supply voltage, process and clock frequency the designer has to do some calculations so that the layout engineers can, in turn, do their calculations to work out the 'bulk-up' capacitance needed for each gate. A gate with a lot of capacitance load could need bigger than minimum input transistors (in order that the load could be discharged in time). This in turn increases the load on the gates driving that gate's inputs. So it can happen, especially in high frequency designs, that the gate sizing keeps on increasing, and this would have to be solved somehow or other.

Evolution

With the advent of CMOS, the precharge transistor could be changed to PMOS, which allows the gate's output to charge right up to the high level of the clock line, thus improving the signal swing and noise margin. This technique is used in domino logic.

References

* Hatt R. J., Jackets A. E. & Jarvis D. B. of Associated Semiconductor Manufacturers "Four-phase Logic Circuits using Integrated m-o-s Transistors" "Mullard Technical Communication": No 99 May 1969
* Komarek, James A. "Phase logic" "United States Patent 3935474"
* Yen, Y. T. "A Mathematical Model Characterizing Four-Phase MOS Circuits for Logic Simulation" "IEEE Transactions on Computers": C-17 Sept. 1968
* Yen, Y. T. "Intermittent Failure Problems of Four-Phase MOS Circuits" "IEEE Journal of Solid-State Circuits": SC-4 No. 3 June. 1969


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