Intel 8253

The Intel 8253 and 8254 are Programmable Interval Timers (PITs), which perform timing and counting functions. They are found in all x86 PCs.

History

In modern times, this PIT is not included as a separate chip in an x86 PC. Rather, its functionality is included as part of the motherboard's southbridge chipset. In some modern chipsets, this change may show up as measurable timing differences in accessing a PIT using the x86 I/O address space. Reads and writes to such a PIT's registers in the I/O address space may complete much faster.

Newer x86 PITs include a counter through the Advanced Configuration and Power Interface (ACPI), a counter on the Local Advanced Programmable Interrupt Controller (Local APIC), and a Time Stamp Counter (TSC) introduced on the Pentium.

Features

The timer has three counters, called channels. Each channel can be programmed to operate in one of six modes. Once programmed, the channels can perform their tasks independently. The timer is usually assigned to IRQ-0 (highest priority hardware interrupt) because of the critical function it performs and because so many devices depend on it.

Typical Components

Counters

There are 3 counters (or timers), which are labeled as Counter 0, Counter 1 and Counter 2. Each counter has 2 input pins - CLK (clock input) and GATE - and 1-pin, OUT, for data output. The 3 counters are 16-bit down counters independent of each other, and can be easily read by the CPU.

The first counter (selected by setting A1=A0=0, see Control Word Register below) helps generate an 18.2 Hz clock signal. The second counter (A1=0, A0=1) assists in generating timing, which will be used to refresh the DRAM memory. The last counter (A1=1, A0=0) generates tones for the PC speaker.

Besides the counters, a typical Intel 8253 microchip also contains the following components:

Data/Bus Buffer

This block contains the logic to buffer the data bus to / from the microprocessor, and to the internal registers. It has 8 input pins, usually labelled as D7..D0, where D7 is the MSB.

Read/Write Logic

The Read/Write Logic block has 5 pins, which are listed below. Notice that /X denotes an active low signal.

* /RD: read signal
* /WR: write signal
* /CS: chip select signal
* A0, A1: address lines

Operation mode of the PIT is changed by setting the above hardware signals. For example, to write to the Control Word Register, one needs to set /CS=0, /RD=1, /WR=0, A1=A0=1.

Control Word Register

This register contains the programmed information which will be sent (by the microprocessor) to the device. It defines how the PIT logically works.

To initialize the counters, the microprocessor must write a control word (CW) in this register. This can be done by setting proper values for the pins of the Read/Write Logic block and then by sending the control word to the Data/Bus Buffer block.

The control word contains 8 bits, labeled D7..D0 (D7 is the MSB).

Bit# D7 D6 D5 D4 D3 D2 D1 D0Name SC1 SC0 RW1 RW0 M2 M1 M0 BCD---- -------- ---------- ----------- ------------------------Func. Select Read/Write Select =0, 16-b binary counter Counter Mode =1, 4-decade BCD counter

The following table describes how to use the Read/Write bits (RW1, RW0).

RW1 RW0 Description--- --- ------------------------------------------------ 0 0 Counter Latch Command 0 1 Read/Write the least significant byte (LSB) only 1 0 Read/Write the most significant byte (MSB) only 1 1 Read/Write LSB first, followed by MSB

Details about other bits will be provided in the next section.

When setting the PIT, the microprocessor first sends a control message, then a count message to the PIT. The counting process will start after the PIT has received these messages, and, in some cases, if it detects the rising edge from the GATE input signal.

On most PCs, the address for the Control Word Register is 043 hex, and 040h, 041h, 042h for each counter, respectively.

Operation Modes

The D3, D2, and D1 bits of the Control Word set the operating mode of the timer. There are 6 modes in total; for modes 2 and 3, the D3 bit is ignored, so the missing modes 6 and 7 are aliases for modes 2 and 3. Notice that, for modes 0, 2, 3 and 4, GATE must be set to HIGH to enable counting. For mode 5, the rising edge of GATE starts the count. For details on each mode, see the reference links.

Mode 0 (000): Interrupt on Terminal Count

In this mode, the counter will start counting from the initial COUNT value loaded into it, down to 0. Counting rate is equal to the input clock frequency.

The OUT pin is set low after the Control Word is written, and counting starts one clock cycle after the COUNT programmed. OUT remains low until the counter reaches 0, at which point OUT will be set high until the counter is reloaded or the Control Word is written.

Mode 1 (001): Hardware-Triggered One Shot

OUT will be initially high. OUT will go low on the CLK pulse following a trigger to begin the one-shot pulse, and will remain low until the Counter reaches zero. OUT will then go high and remain high until the CLK pulse after the next trigger.

After writing the Control Word and initial count, the Counter is armed. A trigger results in loading the Counter and setting OUT low on the next CLK pulse, thus starting the one-shot pulse. An initial count of N will result in a one-shot pulse N CLK cycles in duration.

The one-shot is retriggerable, hence OUT will remain low for N CLK pulses after any trigger. Theone-shot pulse can be repeated without rewriting the same count into the counter. GATE has no effect on OUT.If a new count is written to the Counter during a oneshot pulse, the current one-shot is not affected unless the counter is retriggered. In that case, the Counter is loaded with the new count and the oneshot pulse continues until the new count expires.

Mode 2 (x10): Rate Generator

In this mode, the device acts as a divide-by-n counter, which is commonly used to generate a real-time clock interrupt.

Like other modes, counting process will start the next clock cycle after COUNT is sent. OUT will then remain high until the counter reaches 1, and will go low for one clock pulse. OUT will then go high again, and the whole process repeats itself.

The time between the high pulses depends on the preset count in the counter's register, and is calculated using the following formula:

Value to be loaded into counter = $\{it\; f\_\{input\; over\; \{it\; f\_\{output$

Note that the values in the COUNT register range from $n$ to 1; the register never reaches zero.

Mode 3 (x11): Square Wave Generator

This mode is similar to mode 2. However, the duration of the high and low clock pulses of the output will be different from mode 2.

Suppose n is the number loaded into the counter (the COUNT message), the output will be
* high for $n\; over\; 2$ counts, and low for $n\; over\; 2$ counts, if n is even.
* high for $n+1\; over\; 2$ counts, and low for $n-1\; over\; 2$ counts, if n is odd.

Mode 4 (100): Software Triggered Strobe

After Control Word and COUNT is loaded, the output will remain high until the counter reaches zero. The counter will then generate a low pulse for 1 clock cycle (a strobe) - after that the output will become high again.

Mode 5 (101): Hardware Triggered Strobe

This mode is similar to mode 4. However, the counting process is triggered by the GATE input.

After receiving the Control Word and COUNT, the output will be set high. Once the device detects a rising edge on the GATE input, it will start counting. When the counter reaches 0, the output will go low for one clock cycle - after that it will become high again, to repeat the cycle on the next rising edge of GATE.

Programming Considerations

On x86 PCs, many video card BIOS and system BIOS will reprogram the second counter for their own use. Reprogramming typically happens during video mode changes, when the video BIOS may be executed, and during system management mode and power saving state changes, when the system BIOS may be executed. This prevents any serious alternative uses of the timer's second counter on many x86 systems.

The timer that is used by the system on x86 PCs is Channel 0, and its clock ticks at a theoretical value of 1193181.6666... Hz, i.e. one third of the NTSC color subcarrier frequency. This is a holdover of the very first CGA PCs - they derived all necessary frequencies from a single quartz crystal, and to make TV output possible, this quartz had to run at a multiple of the NTSC color subcarrier frequency.

As stated above, Channel 0 is implemented as a counter. Typically, the initial value of the counter is set by sending bytes to the Control, then Data I/O Port registers (the value 36h sent to port 43h, then the low byte to port 40h, and port 40h again for the high byte). The counter counts "down" to zero, then sends a hardware interrupt (IRQ 0, INT 8) to the CPU. The counter then resets to its initial value and begins to count down again. The fastest possible interrupt frequency is a little over a megahertz. The slowest possible frequency, which is also the one normally used by computers running MS-DOS or compatible operating systems, is about 18.2 Hz. Under these real mode operating systems, the BIOS accumulates the number of INT 0 calls that it receives in real mode address 0000:046c, which can be read by a program.

As a timer counts down, its value can also be read directly by reading its I/O port "twice", first for the low byte, and then for the high byte. The first read latches the value, so that both bytes read will belong to one and the same value.

See also

* Advanced Configuration and Power Interface
* Local APIC
* MCS-85 Family
* Programmable Interval Timer
* Time Stamp Counter

External links

* [http://bochs.sourceforge.net/techspec/intel-82c54-timer.pdf.gz 82C54 Datasheet]
* [http://www.sharpmz.org/mz-700/8253ovview.htm Overview of the Intel 8253 PIT chip]
* [http://www.sharpmz.org/mz-700/memio.htm Intel 8253 complete datasheets]

References

*Gilluwe, Frank van. "The Undocumented PC". A-W Developers Press, 1997. ISBN 0-201-47950-8