SGI Challenge

The Challenge, code named "Eveready" (deskside models) and "Terminator" (rackmount models), is a family of server computers and supercomputers developed and manufactured by Silicon Graphics in the early to mid-1990s that succeeded the earlier Power (not to be confused with the IBM POWER) series systems. The Challenge was later succeeded by the NUMAlink-based Origin 200 and Origin 2000 in 1996.

Models

There are three distinctive models of the Challenge. The first model, simply known as the "Challenge" used the 64-bit R4400. With the introduction of the R8000, the Challenge was upgraded to support more processors and memory as well as featuring support for this new processor. Such systems are known as the "POWER Challenge". During the final years of the Challenge architecture's useful life, the line was upgraded to support R10000 microprocessors. Older Challenge systems using the R10000 were known as the "Challenge 10000", while the newer POWER Challenge systems using the R10000 were known as the "POWER Challenge 10000".

Models suffixed with "GR" (Graphics Ready) could support the RealityEngine and InfinityReality graphics subsystems. Standard models were either servers or supercomputers with no graphics support.

Challenge

POWER Challenge 10000

The POWER Challenge 10000 referred to POWER Challenge-based systems that used the R10000 microprocessor. These models were introduced in January 1996, succeeding the R4400-based Challenge and the R8000-based POWER Challenge, although such systems co-existed with the POWER Challenge 10000 for some time. To support the new R10000s, a new CPU board, the "IP25" was introduced. The new CPU board, like previous IP19 CPU board, support four processors each and their associated secondary caches.

CHALLENGEarray

The CHALLENGEarray and POWER CHALLENGEarray is a cluster of Challenge or POWER Challenge servers respectively. The CHALLENGEarray supports 2 to 288 R10000 processors while the POWER CHALLENGEarray supports 2 to 144 R8000 processors and up to 128 GB of memory. The POWER CHALLENGEarray was introduced on 15 November 1994.

Other models

Other systems from Silicon Graphics that used the "Challenge" brand were the Challenge M and the Challenge S. These systems were repackaged Silicon Graphics Indigo2 and Indy workstations that were not configured with the graphics hardware that made them useful as workstations. These systems were Challenges in name only and have no architectural similarity with the multiprocessing Challenges, although they had cases with the same blue hue as proper Challenges. They were branded as such in order for the systems to be marketed as part of the Challenge server family, positioned as entry level servers.

Description

The deskside enclosure is predominately black with a vertical blue strip on right side. The rackmount enclosure is black, but the front is blue with a horizontal black strip in the middle where the system controller display is mounted. Deskside systems have a width of 54 cm (21 inches), a height of 65 cm (26 inches), a depth of 74 cm (29 inches) and a weighs a minimum of 89 kg (195 lbs).* [http://techpubs.sgi.com/library/manuals/1000/007-1732-060/pdf/007-1732-060.pdf M. Schwenden. Deskside POWER CHALLENGE and CHALLENGE L Owner’s Guide, 23 April 1996, document number: 007-1732-060. Silicon Graphics, Inc.] ] Rackmount systems have a width of 69 cm (27 inches), a height of 159 cm (62.3 inches), a depth of 122 cm (48 inches) and weighs a maximum of 544 kg (1200 lbs). [http://techpubs.sgi.com/library/manuals/1000/007-1735-050/pdf/007-1735-050.pdf Greg Morris and Pablo Rozal. POWER CHALLENGE and CHALLENGE XL Rackmount Owner's Guide, 23 April 1996, document number: 007-1735-050. Silicon Graphics, Inc.] ]

Rackmount systems have a 1,900 watt power supply.

Architecture

The Challenge is a shared-memory multiprocessor computer. The system is based on nodes, which are implemented as boards that plug into a midplane containing Ebus slots and the POWERpath-2 "Ebus" bus, a system bus that the nodes use to communicate with other nodes. The POWERpath-2 bus consists of a 256-bit path for data and a 40-bit path for addressing clocked at 47.6 MHz (21-nanosecond cycle), providing 1.2 GB/s of sustained bandwidth.

The midplane in DM and L models contains five Ebus slots that can support a combination of three CPU, one memory or two POWERchannel-2 interface boards. The midplane also contains five VME expansion slots.

The midplane in XL models contains fifteen Ebus slots that can support a combination of nine CPU, eight memory or five POWERchannel-2 interface boards. The midplane also contains six VME expansion slots and three power board slots.

Boards

The Challenge uses a board set known as the POWERpath-2 board set, code named "Everest". The boards that make up this board set are the IP19, IP21, IP25 CPU boards, the MC3 memory board and the IO4 POWERchannel-2 interface board.

MC3

Memory is provided by the MC3 memory board, which contains thirty-two single in-line memory module (SIMM) slots and two leaf controllers. Fast page mode (FPM) error correcting code (ECC) SIMMs with capacities of 16 MB (known as the "high-density" SIMM) and 64 MB (known as the "super-density" SIMM) are supported, enables the board to provide 64 MB to 2 GB of memory. The SIMMs are installed in groups of four.

The memory is organized into eight banks, with four banks forming a leaf. The memory can be interleaved, if there are more than two or more leaves are present in the system. The memory bus is 576-bit wide, with a 512-bit path for data and a 64-bit path for ECC. The memory is controlled by the two leaf controllers. Each leaf controller manages four banks of memory and half of a memory transaction. It is therefore connected to 256 bits of the memory bus and 128 bits of the POWERpath-2 bus.POWER CHALLENGE Technical Report. Silicon Graphics, Inc.]

Memory transactions are 128-byte wide, the same width as the cache line of the MIPS microprocessors used. A memory read is completed in two cycles of the memory clock, and is buffered by the leaf controllers before it is placed in a sent over the POWERpath-2 bus in four cycles of the POWERpath-2 bus clock.

The SIMMs are protected by ECC, and the ECC implementation can correct single-bit errors and detect double-bit errors. The SIMMs also contain built-in self-test circuitry, which tests the SIMM during power on or reset and alerts the firmware, which disables the bank(s) of memory containing faulty SIMM(s), if faults are detected.

References